An Approach to Design Advanced Standard Encryption Algorithm Using Hardware / Software Co-design Methodology

An Advanced Standard Encryption Algorithm (AES) is widely used in modern consumer electronic products for security. The IEEE 802.15.4 Low-Rate wireless sensor networks also use AES algorithm where low power consumption is the priority. To reduce the time taken for encryption of huge data, the algorithm has to be implemented in hardware. To meet the requirement for low area the algorithm has to be implemented in software. Hence, a balance has to be achieved between hardware and software implementations in terms of area and speed, so as to improve the overall performance of the system. Also with the co-design methodology total thermal power dissipation is reduced. In this paper, 128 bit AES algorithm is implemented with hardware in combination with software using Altera NIOS II Processor platform. Altera’s Quartus II environment is used for design of the system. Cyclone II FPGA is used as a development platform. Software program is written in C language. NIOS II Integrated Development Environment (IDE) is used to integrate hardware and software together. By adopting hardware / software co-design methodology for implementation of AES, results show that a considerable improvement in speed can be achieved as compared to software only approach. Further, the significant reduction in area is achieved as compared to hardware only approach. By the approach of co-design an optimized design in terms of speed and area is achieved and also the thermal power dissipation is reduced.